Classical semiconductor scaling, typically known as a device shrink, is currently supplemented by effective scaling using techniques such as stress memorization. Stress memorization techniques are being used to speed carrier mobility in transistor channels, enabling higher drive currents. Stress or strain in a device may have components in three directions, parallel to the metal-oxide-semiconductor (MOS) device channel length, parallel to the device channel width, and perpendicular to the channel plane. The strains parallel to the device channel length and width are called in-plane strains. Research has revealed that a bi-axial, in-plane tensile strain field can improve NMOS (N-channel MOS transistor) performance, and compressive strain parallel to channel length direction can improve PMOS (P-channel MOS transistor) device performance.
One way to develop strain is by using a graded SiGe epitaxy layer as a substrate on which a layer of relaxed SiGe is formed. A layer of silicon is formed on the relaxed SiGe layer. MOS devices are then formed on the silicon layer, which has inherent strain. Since the lattice constant of SiGe is larger than that of Si, the Si film is under biaxial tension and thus the carriers exhibit strain-enhanced mobility. The lattice spacing mismatch between the SiGe layer causes the underlying layer to develop an in-plane stress to match the lattice spacing. However, with entire underlying layers under stress, defects causing junction leakage may be more prevalent.
Strain can also be applied by forming a strained barrier layer, such as a nitride layer, on a MOS device. However, the barrier layer may not produce sufficient stress to produce the desired results. The conventional method of forming strained barrier layers suffers drawbacks, and the effect is limited by the properties of the barrier layer. For example, the thickness of the strained barrier layer is limited due to the subsequent gap filling difficulty caused by the thick barrier layer. Therefore, the strain applied by the barrier layer is limited. In addition, forming a strained barrier layer that has customized strains for different devices, such as PMOS and NMOS devices, is particularly complex and costly.
Turning to FIG. 1, a method of forming a tensile strained silicon channel is illustrated. A buffered Si layer 102 is epitaxially grown on semiconductor substrate 100. A step graded SiGe layer 104 is epitaxially grown between the buffered Si layer 102 and a relaxed SiGe layer 106. A strained Si layer 108 is epitaxially grown on the relaxed SiGe layer 106. Gate dielectric 112 is formed on the strained Si layer 108. Further, source/drain regions 116 and gate electrode 120 have silicided areas 110.
Some disadvantages to this and other prior art methods may include poor device performance in advancing technologies, such as the 32 nm node. Among the poor device performance issues is poor junction leakage, severe SiGe loss, and relaxation of strained layers.